Integrated circuits (chips) comprise many different components that must have electrical connections therebetween in order to interoperate. Typically, the chip real estate is divided into different regions with each particular component being assigned a particular region of the “floorplan.” For example, separate regions are reserved for a floating point unit, a memory controller, a processor core, etc. Herein, these regions are referred to as blocks. Typically, a thin channel separates the blocks.
In order for the different components to interoperate, thousands of electrical interconnections are needed between the components. Typically, the interconnections are implemented in metal layers above the chip substrate. Commercial routing tools exist to determine interconnection routes in the metal layers. Typically, the commercial router attempts to determine routes that minimize the amount of metal used.
Each of the interconnections requires a “pin assignment” associated with the component at each end of the interconnection. That is, each interconnection requires a source pin to electrically connect to the source component and a sink pin to electrically connect to the destination component. Typically, a pin assignment describes physical information such as an “x, y” location, a particular metal layer, and a physical dimension for the pin.
One technique for establishing pin assignments is to have a person input pin assignments during a floorplanning stage. Then, the commercial routing tool determines interconnection routes to connect respective source and sink pins. As previously mentioned, the router usually attempts to determine an overall solution that minimizes metal utilization.
After routes have been determined, a timing analysis is performed to determine if the interconnection routes meet timing constraints. Unfortunately, the timing analysis generally indicates that many of the interconnection routes fail to meet a timing constraint. A consequence of this timing violation is that the initial pin assignments need to be changed. However, once the pin assignments are changed, the routing and timing must be re-performed. Often, it takes many iterations of this cycle before satisfactory pin assignments are found. A consequence of this iteration is that the chip release date is delayed. In today's competitive marketplace, time to market is important to the success or failure of a chip.
As chips become more complex and compact, the consequences of pin re-assignments becomes more severe. For example, high performance microprocessors have a substantial amount of custom layout in order to achieve the highest possible performance in the smallest die size. However, pin re-assignments lead to route changes. A possible consequence of routing changes is a need to change the custom layout. Changes to the custom layout are very undesirable due to the time, difficulty, and expense. Moreover, changes to a single route could ripple to hundreds of nearby routes, especially if the track routing is dense. Because high-performance, custom layouts often employ dense routing, the chance of routing changes due to a pin-reassignment is quite high.
Because of these and potentially other drawbacks, this approach does not provide wholly satisfactory results. Consequently, an improved method and system for determining pin assignments for interconnections during an integrated circuit design process is desired.